To estimate the operable life of integrated circuits, they undergo burn-in testing. During burn-in testing, excess stresses are applied to the integrated circuits in an operating environment that is worse than the expected normal operating environment. This type of testing accelerates aging of the integrated circuits to determine to a reasonable certainty whether the integrated circuits will perform as expected for their anticipated life.
Burn-in testing may be performed at the wafer-level, i.e., before the integrated circuits are packaged. U.S. Pat. No. 6,060,895 to Soh et al. discloses a wafer-level dielectric testing structure that includes a heating element that is part of the integrated circuit being tested. The heating element is formed as a layer above a tunnel oxide layer of the integrated circuit. The heating element helps to accelerate endurance testing. However, the testing is conducted before the integrated circuit is packaged.
Burn-in testing may also be performed at the package-level, i.e., after the integrated circuits are packaged. The packaged integrated circuits are placed on burn-in test boards, each of which includes burn-in test circuits and pads for receiving various types of test voltages. The burn-in test circuits include burn-in instructions for operating the integrated circuits and for collecting and evaluating data therefrom. The burn-in test boards and the packaged integrated circuits are then placed in a burn-in chamber.
Burn-in testing is conducted at elevated temperatures within the burn-in chamber for specified periods of time in a way that exposes “infant mortality failures.” The integrated circuits that fail as a result of fabrication variation, and those that fail early in the test procedure, indicate a much earlier than expected failure if used under actual operating conditions. Burn-in testing can also be used to expose integrated circuits that do not apparently have fabrication flaws, but nevertheless, would fail at unexpectedly early times in their service lives.
Burn-in testing of integrated circuits in a burn-in chamber is a slow and expensive process. Large burn-in chambers are required to accommodate multiple burn-in test boards. There is also a limited throughput of the burn-in chambers, and a limited amount of integrated circuits can be mounted on the burn-in test boards.
Another drawback of testing integrated circuits in a burn-in chamber is that all the circuits and components within the burn-in chamber are stressed by the high temperatures. This causes the burn-in boards to degrade over time, for example. Moreover, the entire packaged integrated circuits are stressed even though selected areas thereof may actually be tested. For example, U.S. Pat. No. 5,309,090 to Lipp discloses a packaged integrated circuit including heating means, along with sensing and control means, for heating the integrated circuit to a desired temperature for purposes of burn-in testing. However, all of the integrated circuit is heated.